In this process, we start with a substrate of high resistivity n-type material and then create both n-well and p-well regions. Through this process, it is possible to preserve the performance of the n-transistors without compromising p-transistors. Doping control is more readily achieved and some relaxation in manufacturing tolerance results. This is particularly important as far as latchup is concerned.
The twin-tub process allows two separate tubs to be implanted into very lightly doped silicon. This allows the doping profiles in each tub region to be tailored independently so that neither type of device will suffer from excessive doping effects. The lightly doped silicon is an epitaxially grown layer on a heavily doped silicon substrate. The substrate can be either n-type or p-type. The process sequence for a CMOS twin-tub process is discussed as:. The twin-tub CMOS technology provides the basis for separate optimization of the p-type and n-type transistors.
As the name suggest it is a process where the transistors are fabricated on an insulator. Two main insulators are SiO 2 and sapphire. SiO 2 is laid out by oxidation process done exposing the substrate to high-quality oxygen and hydrogen in an oxidation chamber at approximately 0 c.
Step 3 — Growing of Photoresist: At this stage to permit the selective etching, the SiO2 layer is subjected to the photolithography process. In this process, the wafer is coated with a uniform film of a photosensitive emulsion. Step 4 — Masking: This step is the continuation of the photolithography process. In this step, a desired pattern of openness is made using a stencil. This stencil is used as a mask over the photoresist.
The substrate is now exposed to UV rays the photoresist present under the exposed regions of mask gets polymerized. Step 5 — Removal of Unexposed Photoresist: The mask is removed and the unexposed region of photoresist is dissolved by developing wafer using a chemical such as Trichloroethylene. Step 6 — Etching: The wafer is immersed in an etching solution of hydrofluoric acid, which removes the oxide from the areas through which dopants are to be diffused. Step 7 — Removal of Whole Photoresist Layer: During the etching process , those portions of SiO2 which are protected by the photoresist layer are not affected.
The photoresist mask is now stripped off with a chemical solvent hot H2SO4. Step 8 — Formation of N-well: The n-type impurities are diffused into the p-type substrate through the exposed region thus forming an N- well. Step 10 — Deposition of Polysilicon: The misalignment of the gate of a CMOS transistor would lead to the unwanted capacitance which could harm circuit.
Polysilicon is used for formation of the gate because it can withstand the high temperature greater than 0 c when a wafer is subjected to annealing methods for formation of source and drain.
Polysilicon is deposited by using Chemical Deposition Process over a thin layer of gate oxide. This thin gate oxide under the Polysilicon layer prevents further doping under the gate region.
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